1. Field of the Invention
The present invention relates to a semiconductor test board, and more particularly, to a semiconductor test board for a fine pitch ball grid array package.
2. Description of the Related Art
With increases in the function, integration, and number of pins of semiconductor devices, it becomes more important to use an excellent test board with improved characteristics, which can test the device under optimum conditions.
Types of packages include a quad flat package (QFP), dual in-line package (DIP), plastic leaded chip carrier (PLCC), and ball grid array (BGA). Especially for the BGA, the number of pins increases while the size of the test board decreases. However, technology for producing test hardware for testing the package is far behind this increase in pin quantity and reduction in size.
A light weight fine ball grid array (FBGA) package, having a plurality of pins, is a leading semiconductor chip. However, there is a limit in producing a test board for the FBGA package using conventional producing technology. Accordingly, when the distance between balls, namely the ball pitch, is under a predetermined value, it is impossible to directly draw a pattern on the test board for supplying current to holes which are connected to the balls. This is because the ball pitch is small so that it is difficult to form the pattern in a non-contact state with the holes.
As a result, a sub test board or a socket board is added on a main test board in the conventional test board for the FBGA package for solving the problem of the direct drawing.
However, the sub test board causes several difficulties. Since a test socket on which the semiconductor package is mounted cannot be directly connected to the main test board, incomplete contact may occur at the contact points between the sub test board and main test board. In addition, resistance values increase, causing problems in a high speed test and an analog test.
FIG. 1 is a sectional view illustrating a conventional test board for a semiconductor memory.
A test board 100 is an apparatus for interfacing between a test system (not shown), which tests electric characteristics of semiconductor packages, and a semiconductor package 150 to be tested.
Referring to FIG. 1, the test board 100 is formed of a performance board 110 on which a guide panel 120 is mounted and supported by supporters 115. In this case, the performance board 110 is inserted into the test system, and a device under test (DUT) board 130 is inserted into the guide panel 120. The corresponding semiconductor package 150 is connected to the DUT board 130 through a socket 140. In this case, it is preferable that means other than the socket 140 connect the DUT board 130 and the semiconductor package 150.
Since the performance board 110 and the DUT board 130 are connected through cables 125, electric signals for testing the semiconductor package 150 are transferred from the performance board 110 to the DUT board 130 through the cables 125. The electric signals transferred to the DUT board 130 are input to the semiconductor package 150 through the socket 140.
FIG. 2 is a top plan view illustrating the test board of FIG. 1.
Referring to FIG. 2, the DUT board 130 is placed on the performance board 110 of a test board 200. The DUT board 130 is formed of a socket contact unit 210 and a channel region 220. In this case, the socket (not shown) on which the semiconductor package (not shown) is mounted is connected to the DUT board 130 made of a plurality of joined layers (not shown). The channel region 220 has channels to which pogo pins are connected for transferring the electric signals for testing the package.
Holes on the socket contact unit 210 are connected to the channels CH1, CH2, CH3, and CH 4 of the channel region 220 through pattern lines PLINE1, PLINE2, PLINE3, and PLINE4 that perform as electric passages. In this case, the socket contact unit 210 is connected to the pins of the socket on which the semiconductor package is mounted.
When the socket having the semiconductor package is connected in the conventional test board 200, the pins of the socket are directly connected to the upper surface of the socket contact unit 210 of the test board 200.
The holes are formed from the upper surface of the socket contact unit 210 to the bottom of the socket contact unit 210, namely a last layer, by passing through all the layers. The pattern lines PLINE1, PLINE2, PLINE3, and PLINE4 are formed on each layer for connecting the holes to the channels at the edges of the DUT board 130. That is, the first pattern line PLINE1 is formed on the top layer of the socket contact unit 210 for connecting one hole to the first channel CH1, and the second pattern line PLINE2 is formed on a second layer of the socket contact unit 210 for connecting another hole to the second channel CH2. In the same manner, the third and fourth pattern lines PLINE3 and PLINE4 are formed on third and fourth layers for connecting holes to the third and fourth channels CH3 and CH4.
In this case, the distance between the holes, namely the ball pitch, on the top layer of the socket contact unit 210 is the same as on the bottom layer, in the conventional test board 200.
It is a trend that the ball pitch becomes smaller. When the socket contact unit 210 of the test board 200 has the ball pitch of less than a predetermined size, for example about 0.65 mm, it is difficult to directly draw the pattern lines on the layers of the socket contact unit 210 and to produce the test board 200. Therefore, a sub test board is produced for mounting the socket, and the sub test board having the socket is mounted on the test board, thereby separately mounting the socket.
FIG. 3 is an enlarged view of a portion of the socket contact unit shown in FIG. 2.
FIG. 3 illustrates a socket contact unit having a ball pitch BP of 0.65 mm. In contrast to a practical board, the test board has the socket contact unit, which is formed by coupling more than six layers. Accordingly, the sizes of the holes on the socket contact unit of the test board become gradually smaller, making it difficult to form the pattern lines for connecting the holes in the socket contact unit to the channels outside of the socket contact unit.